MBM29F800TA-70PFTN
IC,EEPROM,NOR FLASH,512KX16/1MX8,CMOS,TSSOP,48PIN,PLASTICMBM29F800TA-70PFTN
IC,EEPROM,NOR FLASH,512KX16/1MX8,CMOS,TSSOP,48PIN,PLASTIC
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製造商零件號 # : MBM29F800TA-70PFTN
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包裝/封裝: TSOP-48
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製造商: Fujitsu Limited
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MBM29F800TA-70PFTN 數據表
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感興趣的部分
MBM29F800TA-70PFTN 詳細說明
■ GENERAL DESCRIPTION The MBM29F800TA/BA is a 8M-bit, 5.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K words of 16 bits each. The MBM29F800TA/BA is offered in a 48-pin TSOP(I) and 44-pin SOP packages. This device is designed to be programmed in-system with the standard system 5.0 V VCC supply. 12.0 V VPP is not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. The standard MBM29LV800TA/BA offers access times 55 ns and 90 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. ■ FEATURES • Single 5.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) 44-pin SOP (Package suffix: PF) • Minimum 100,000 write/erase cycles • High performance 55 ns maximum access time • Sector erase architecture One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes. Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture T = Top sector B = Bottom sector • Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Low Vcc write inhibit ≤ 3.2 V • Erase Suspend/Resume Suspends the erase operation to allow a read data in another sector within the same device • Hardware RESET pin Resets internal state machine to the read mode • Sector protection Hardware method disables any combination of sectors from write or erase operations • Temporary sector unprotection Temporary sector unprotection via the RESET pin.
主要特徵
- Single 5.0 V read, write, and erase
- Minimizes system level power requirements
- Compatible with JEDEC-standard commands
- Uses same software commands as E2PROMs
- Compatible with JEDEC-standard world-wide pinouts
- 48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
- 44-pin SOP (Package suffix: PF)
- Minimum 100,000 write/erase cycles
- High performance
- 55 ns maximum access time
- Sector erase architecture
- One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes.
- Any combination of sectors can be concurrently erased. Also supports full chip erase.
- Boot Code Sector Architecture
- T = Top sector
- B = Bottom sector
- Embedded EraseTM Algorithms
- Automatically pre-programs and erases the chip or any sector
- Embedded ProgramTM Algorithms
- Automatically writes and verifies data at specified address
- Data Polling and Toggle Bit feature for detection of program or erase cycle completion
- Ready/Busy output (RY/BY)
- Hardware method for detection of program or erase cycle completion
- Low Vcc write inhibit ≤ 3.2 V
- Erase Suspend/Resume
- Suspends the erase operation to allow a read data in another sector within the same device
- Hardware RESET pin
- Resets internal state machine to the read mode
- Sector protection
- Hardware method disables any combination of sectors from write or erase operations
- Temporary sector unprotection
- Temporary sector unprotection via the RESET pin.
規格
以下是所選零件的基本參數,涉及零件的特性及其所屬類別。
| Part Life Cycle Code | Active | Reach Compliance Code | compliant |
| Access Time-Max | 70 ns | Alternate Memory Width | 8 |
| Boot Block | TOP | Command User Interface | YES |
| Data Polling | YES | Endurance | 100000 Write/Erase Cycles |
| JESD-30 Code | R-PDSO-G48 | Memory Density | 8388608 bit |
| Memory IC Type | FLASH | Number of Sectors/Size | 1,2,1,15 |
| Number of Terminals | 48 | Number of Words | 524288 words |
| Number of Words Code | 512000 | Operating Temperature-Max | 85 °C |
| Operating Temperature-Min | -40 °C | Organization | 512KX16 |
| Package Body Material | PLASTIC/EPOXY | Package Code | TSSOP |
| Package Equivalence Code | TSSOP48,.8,20 | Package Shape | RECTANGULAR |
| Package Style | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH | Parallel/Serial | PARALLEL |
| Power Supplies ! | 5 V | Qualification Status ! | Not Qualified |
| Ready/Busy | YES | Sector Size | 16K,8K,32K,64K |
| Standby Current-Max | 0.000005 A | Supply Current-Max | 0.05 mA |
| Supply Voltage-Nom (Vsup) | 5 V | Surface Mount ! | YES |
| Technology | CMOS | Temperature Grade ! | INDUSTRIAL |
| Terminal Form ! | GULL WING | Terminal Pitch ! | 0.5 mm |
| Terminal Position | DUAL | Toggle Bit | YES |
| Type | NOR TYPE |
數據表 PDF
數據表記錄了器件的特性、絕對最大額定值、應用等,這對於作為器件特定應用的整體指南大有裨益。
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